We are happy to announce Capstone 6.0.0-Alpha11.

Highlights

This is another patch release with multiple instruction fixes and bug fixes.

This release adds an AGENTS.md file and developer AI guidelines.

API changes/additions

• x86: Support alternative disassembly for JO/JNO operands in 64-bit mode. This adds two modes for x86: CS_MODE_X86_AMD and CS_MODE_X86_INTEL. Setting either of these flags will currently only affect the JO/JNO instructions. Please check the release guide for more details. The default behavior of the x86 module did not change.
• Xtensa: Gate ESP32-S3 and HIFI3 instructions behind CS_MODE_XTENSA_ESP32S3

New instruction

• PowerPC: add mcrxr instruction support

Instruction fixes

• AArch64: report NZCV access for MRS/MSR of NZCV
• HHPA: Correct name of r0 register - flags -> r0
• x86: use effective address size for the loop counter register
• x86: fix VMOVUPS memory operand access
• PowerPC: Keep BI out of the CTR-only branch predicate
• x86: fix EVEX writemask access in AT&T syntax